Normally, a program is debugged (errors found and eliminated) on a central processing unit, (CPU) or other processing units (PU) that the program is designed to run on. However when a plurality of PUs are placed on a single chip, it is sometimes desirable to limit the memory available to one or more specialized function processing units (SPUs). At that point, the supplemental processor processes those tasks with its highest efficiency. With this methodology, the number of possible PUs placed on a specified size chip is increased
In a conventional system, a debugger will have unlimited access to all of the states in the executable program that is being debugged. The debugger needs to issue read and write commands to a plurality of addresses. Subsequently, the debugger logic modifies the states of executable operations. If the memory or flexibility of the PU is limited, reads and writes may not be possible even if the debugging program employs a master, main or control PU. Furthermore, in order to maximize processing power for specified chip architecture, the main or control PU may not have access to the register state of the SPUs on the chip.
Accordingly, a need exists for a system that efficiently and effectively reduces such problems by developing a procedure to debug a program designed to run on a SPU having limited resources and which does not allow SPU register state access to devices external to the SPU.